Tiled rendering is the process of subdividing (or tiling) a computer graphics image by a regular grid in image space to exploit local spatial coherence in the scene and/or to facilitate the use of limited hardware rendering resources later in the graphics pipeline.
Tiled rendering is sometimes known as a "sort middle" architecture.
In a typical tiled renderer, geometry must first be transformed into screen space and assigned to screen-space tiles. This requires some storage for the lists of geometry for each tile. In early tiled systems, this was performed by the CPU, but all modern hardware contains hardware to accelerate this step. The list of geometry can also be sorted front to back, allowing the GPU to use hidden surface removal to avoid processing pixels that are hidden behind others, saving on memory bandwidth for unnecessary texture lookups.
Once geometry is assigned to tiles, the GPU renders each tile separately to a small on-chip buffer of memory. This has the advantage that composition operations are cheap, both in terms of time and power. Once rendering is complete for a particular tile, the final pixel values for the whole tile are then written once to external memory. Also, since tiles can be rendered independently, the pixel processing lends itself very easily to parallel architectures with multiple tile rendering engines.
Tiles are typically small (16×16 and 32×32 pixels are popular tile sizes), although some architectures use much larger on-chip buffers and can be said to straddle the divide between tiled rendering and immediate mode ("sort last") rendering.
Tiled rendering should not be confused with tiled/nonlinear framebuffer addressing schemes, which make adjacent pixels also adjacent in memory. These addressing schemes are used by a wide variety of architectures, not just tiled renderers.
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